1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory device and a data output circuit. This application claims priority under 35 U.S.C. §119 from Korean Patent Application 2003-64344, filed on Sep. 17, 2003, the contents of which are hereby incorporated by reference in their entirety.
2. Description of the Related Art
A semiconductor memory device (e.g. dynamic random access memory (DRAM)) may employ a data output circuit which outputs data from a selected memory cell. The output circuit may include a data output buffer and a data output driver. The output circuit may have a current drivability that is in conformity with a corresponding output load. The driver strength of the data output driver should be adequate for the output load, in order to substantially reduce skew that limits high frequency performance.
Control of the driver strength, after the completion of production and the shipment of memory products, may be desirable. Thus, semiconductor manufacturers often design chips having controlled driver strength of the data output driver, by using a circuit such as a mode register set (MRS).
FIG. 1 is a circuit diagram of a driver strength code setting circuit. A data output driver includes four output drive units, that are independently controlled and share an output terminal. If the size ratio of the four output drive units is 1:1:2:4, a logic state of control codes S0 and S1 is 00, 01, 10, or 11, by using MRS codes of 2 bits. Accordingly, a driver strength (DS) value of the data output driver can be controlled to four levels (full, ½, ¼, and ⅛). For example, when logic states of a first MRS code MRS CODE 0 and a second MRS code MRS CODE 1 are individually applied as 0,0 and a set control signal PMRS_SET is applied at a high level (e.g. 1), the control codes S0 and S1 are each generated as 0,0 through an operation of the circuit of FIG. 1. As another example, when the logic states of the first MRS code MRS CODE 0 and the second MRS code MRS CODE 1 are individually applied as 0,1 and the set control signal PMRS_SET is applied at a high level (e.g. 1), the control codes S0 and S1 are each generated as 0,1.
In the circuit which generates the control code value S0, an inverter IN1 inverts a logic state of the first MRS code MRS CODE 0 and outputs it as an input of a pass gate PG1. The pass gate PG1 passes the output of the inverter IN1 only when the set control signal PMRS_SET is 1. An output of the pass gate PG1 is inverted by an inverter IN3 of a latch L1 and is provided as an output of the control code S0.
In the circuit of FIG. 1, a power up signal VCCH is applied to a gate of a PMOS transistor PM1. VCCH changes from a low level to a high level by an increase of power source VCC, as shown in FIG. 2. Thus, the control codes S0, S1 are initially set as 0,0. Accordingly, when the power up signal VCCH is at a low level, the PMOS transistor PM1 is turned on and the input terminal of the latch L1 (i.e. the input of the inverter IN3) is at a high level and the output of the inverter IN3 is at a low level. Thus, even though the power up signal VCCH changes to a high level, an initial value of the control codes S0 and S1 are fixed at 0,0, in the circuit of FIG. 1.
The driver strength (DS) value may be controlled to be one of four levels (e.g. full, ½, ¼, and ⅛) by applying MRS codes of 2 bits in the circuit referred to FIG. 1. However, at the time of manufacturing, an initial value of the control codes S0, S1 are fixed to one value set, even without any selection. If the initial values of the control codes S0 and S1 are generated as 01, 10, or 11, the circuit would have to be changed. In other words, a fabrication mask required to fabricate a semiconductor memory device would have to be changed, which would increase manufacturing costs. In other words, since the initial value of the driver strength is fixed at one value at the time of manufacturing, a fabrication mask must be changed if the users require different initial values of the driver strength.